The present invention relates to a semiconductor memory device which has sub bit lines, and more particularly to a dynamic random access memory (DRAM) whose architecture is convenient in higher integration of a memory device.
The higher integration of DRAM has been progressed rapidly. For example, the extent of integration has been doubled in three years. Such higher integration of DRAM has been realized mainly by (i) progress of super fine processing technique and (ii) increase of chip size. Another reason which can not be omitted is an improvement of memory cell structure. As a matter of fact, such improvement of memory cell structure enables higher integration of DRAM than that based upon super fine processing technique. This is clear according to the history of DRAM. First memory cell structure in the history is four (4) transistor-type cell in which four (4) MOS transistors are required to hold data of one (1) bit. Thereafter, three (3) transistor-type cell emerged, and then, after the advent of 16K bit DRAM, one (1) transistor-type cell has been mainly used to date. As apparent from the foregoing, higher integration of DRAM has been realized by an improvement of memory cell structure, i.e., reduction of the number of a transistor which forms a memory cell. In addition to that, in the course of development from 16K bit DRAM to 1M bit DRAM, high integration of DRAM has been realized by mainly, progress of super fine processing technique and improvement of layout in memory cells. After the advent of 1M bit DRAM, high integration of DRAM has been realized and will be realized by adopting unique structure of a memory cell capacitor in which a capacitance is formed in a groove vertically formed in a silicon substrate so that plane size of a capacitor can be minimized. That is, in this case, size reduction of a memory cell can be realized by three dimensionalization of a cell.
In the course of the above-stated development, there has been no substantial improvement or change as to peripheral circuits which are necessary for DRAM and depend upon memory cell pitch, e.g., sense amplifier.
Under such circumstances, higher integration of DRAM based upon improvement of memory cell structure has been progressed day by day. As a result, a gap between peripheral circuits of DRAM and memory cell pitch has been increasing.
Therefore, in the foreseeable future, there may occur a case wherein the extent of integration of DRAM is defined by peripheral circuits.